Makefile Variables

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# 4.2. Makefile Variables

- We can define variables in makefiles to make the writing shorter and the modifications easier.
- Rewriting previous makefile with variables and extra targets.

    CC= gcc
    LD= gcc
    CC_FLAGS = -ansi -Wall -c
    LD_FLAGS = -Wall

    all: foo bar

    foo: foo.o helper.o
        $(LD) $(LD_FLAGS) foo.o helper.o -o foo
    bar: bar.o helper.o
        $(LD) $(LD_FLAGS) bar.o helper.o -o bar

    bar.o: bar.c
        $(CC) $(CC_FLAGS) bar.c
    foo.o: foo.c foo.h
        $(CC) $(CC_FLAGS) foo.c

    clean:
        rm -f *.o foo bar

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